The present invention relates to a successive approximation analog to digital converter for converting an analog signal to a corresponding digital signal. More particularly, the invention relates to an analog to digital converter which is characterized by high accuracy and high conversion speed employs components having low matching tolerances and easily performs digital calibrations.
In a successive approximation analog to digital (A/D) converter of this type, an analog to digital coverter is known in which the calibration is carried out in a digital manner, so that a high accuracy characteristic is obtained with a low accuracy digital to analog (D/A) converter. For example, a monolithic 13 bit A/D converter is disclosed in Session 1: A/D and D/A converters, pages 12 and 13, Digest of Technical Papers, 1980 IEEE International Solid-State Circuits Conference, Feb. 13, 1980. In this A/D converter, a high accuracy local D/A converter is realized by combining a usual successive approximation A/D converter with an analog adder/subtractor, an additional D/A converter for generating an analog calibration value and a calibration code memory circuit such as a ROM (read only memory).
A significant problem encountered when a successive approximation A/D converter is constructed by using such a D/A converter (referred to as DAC), is that high speed operation can not be expected. In the DAC, while it is sufficient that the calibration be performed only with respect to higher order bits from which errors occur, it is required to access a memory circuit such as a ROM or RAM (random access memory) to read out a proper calibration code at each successive approximation operation of the higher order bits. Therefore, there is a disadvantage in that the conversion operation is greatly delayed, when the number of bits is increased in order to improve the accuracy of the A/D conversion.
When an LSI process of the MOS family is used for circuit fabrication, with many advantages such as low power dissipation, high integration density, and facility for realizing a high accuracy sample/hold which is essential to the successive approximation A/D converter, a capacitor array is preferably used as a circuit arrangement for the DAC. In this case, in order to realize an accuracy of 14 bits or more, the unit capacitance can not be reduced very much from the viewpoint of the accuracy of the components, even if the calibration is performed. Considering the settling time of the DAC, the access time of the memory circuit and the settling time of the adder/subtractor, it is more difficult to improve the conversion time of the DAC as higher accuracy is required. Accordingly, the conversion time of the A/D converter is greatly inferior to that of the original A/D converter in which the calibration is not performed. When a high performance A/D converter with an accuracy of 14 bits or more and a conversion speed of 60 ksps (kilo samples per sec) is required, such as an A/D converter for high quality voice processing, such an A/D converter can hardly be realized in the form of LSI or the like.
In order to improve the accuracy of the A/D converter, an analog adder/subtractor with a high accuracy and additional DAC for generating an analog calibration value are required. Usually, it is very difficult to ensure an accuracy of 14 or 15 bits, due to the non-linearity error of the adder/subtractor which is influenced by noise and so on. Thus, the adder/subtractor hinders the improvement of an accuracy of the A/D converter.
Particularly, in order to realize the analog subtracting function, there are required a polarity inverting circuit and an adder/subtractor control function. The requirement also hinders the improvement of accuracy and the reduction of chip area.
As described above, the conventional A/D converter of this type allows little improvement of the converting speed, improvement in the accuracy by calibration is limited, and it is particularly difficult to fabricate the adder/subtractor.